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“Keep innovating Maxim and team. We were early partners of yours and are excited to see you continuing your innovative ways to help deliver both insight and speed. At Alphawave, we pride ourselves on moving fast while not breaking things. Diakopto’s ParagonX software is a key enabler of this approach. ParagonX helps Alphawave accelerate time-to-tapeout and improve design efficiency in leading-edge technology nodes by quickly pinpointing layout issues and bottlenecks, and identifying design and layout improvements. ParagonX is very fast. Analysis of small blocks is immediate. More importantly, ParagonX is able to analyze very large netlists that are impractical to simulate using other tools without compromising accuracy. The large capacity of ParagonX allows Alphawave to accurately validate key electrical targets at the top level of integration and iterate quickly.”

Tony Pialis, CEO

“The Diakopto team are the unsung heroes of the semiconductor industry. The critical tools they provide are accelerating the innovation of high-speed circuits in the most advanced chip technologies. I haven’t met a chip design that doesn’t appreciate their technology.” #keepinnovating

Nafea Bshara, VP/Distinguished Engineer

“With ParagonX, I can find a weak point on a 20GB extract in minutes, taking me right to the coordinates of the problematic area.”

Ken Dyer, Principal Analog Design Engineer

“Much of my time is spent digging into the details of the layout to get the best performance possible for the power, area, and ultimately TIME available. Diakopto’s ParagonX has been indispensable in sifting through the haystack to find the proverbial needle. What would take weeks of trial and error can now be done in one revision – truly game changing.”

Eric Groen, Principal Engineer

“I can personally attest to the importance of a tool like ParagonX for state of the art AMS design. I was instantly more productive once I started using it and couldn’t live without it now.”

Jade Kizer, SerDes Design Architect

“Diakopto’s ParagonX tools are real life savers! We have used ParagonX for the past year, and it has become indispensable for us when debugging parasitic RC layout. We have applied it to literally hundreds of blocks. It just works from the get-go, no setup issues whatsoever and we were productive within half an hour of the initial install. The user interface is very intuitive and extremely easy to understand and use. Taken together this results in a significant reduction in debug time compared to other debug flows. Keep innovating and getting us out of trouble! I can highly recommend the tool for everyone!”

Mikael Sahrling, Principal Engineer
IPG Photonics

“We’re using ParagonX to help analyze and optimize these parasitics to improve our designs. ParagonX has many powerful features that both designers and layout engineers can use to analyze the design. One additional and unexpected benefit we’ve found is that ParagonX’s visualization capability has been a very effective way for designers and layout engineers to communicate about the parasitics affecting design performance.”

Jeff Galloway, Co-founder and CTO
Silicon Creations

“ParagonX is a great productivity tool for anyone who wants to deliver quality designs that push the envelope.”

Boris Murmann, EE Professor
Stanford University

“At Rambus, we are designing state-of-the-art SERDES in leading-edge technologies and always pushing the limits of process performance. With interconnects playing an ever increasing role in deep sub-micron processes, understanding its impact on circuit performance is essential. We have found Diakopto’s ParagonX tool kit essential for quickly understanding the impact of interconnect parasitics on our highest speed circuits. In less than a day, ParagonX enabled us to visualize critical speed paths, assess the contribution of various parasitic elements to their speed, and intelligently optimize our design. Maxim Ershov has also demonstrated he’s a top expert in parasitic extraction and interconnect analysis across a broad array technologies. We found his help essential in getting up to speed on the ParagonX tool and he was able to provide us valuable insight on analysis of our critical nets.” 

Fred Heaton, Senior Director of IP Core Development

“It’s not enough these days to run simulations faster and faster when it’s hard to understand what’s fundamentally going on in the post-layout design. Trying to understand the simulation results is taking more and more of our time. In particular, trying to understand how the parasitics affect the simulation is becoming the dominant activity. Which is exactly where your tool comes into play.”

Tom Krawczyk, VP of Analog Design
Jariet Technologies

“Layout parasitics have become one of the dominant problems in IC design. ParagonX stands alone in superior ease-of-use, analysis speed and in conveying insights that drive design improvements. This has helped us develop higher quality and lower power SerDes IP at a much faster rate.”

Harry Chan, CEO
eTopus Technology

“As we migrate our designs to advanced FinFET technologies, IC layout parasitics have become the dominant source of performance and reliability bottlenecks, as well as delays in our development cycle. ParagonX is a godsend to help us navigate and overcome these challenges. It is extremely fast and easy to use, and provides very intuitive results and deep insights to parasitics-induced problems to drive improvements and optimizations in our designs.”

Mike Kappes, CEO

“ParagonX is a must-have for any company designing high-speed, high-precision or low-power ICs, especially in advanced manufacturing technologies. The semiconductor industry has shifted to a new era where advances in design approach, tools and methodology are needed. ParagonX is an innovative and extremely user-friendly EDA tool with virtually no learning curve for our engineers. This helps us to optimize and enhance our designs much quicker and more reliably, leading to faster customer adoption and time-to-market for us.”

Robert Wang, CEO

“Ferric is focused on cutting-edge technology that saves power, space and cost. To further deliver on this strategy, we have chosen a next-generation tool, developed for this emerging era in which parasitics are the main roadblock to performance, power, cost and time-to-market.”

David Jew, VP of Engineering

“To achieve the absolute lowest power in our wireless IoT solutions, we need to squeeze every ounce of performance and power efficiency out of our designs. ParagonX is an important enabler of our design methodology by giving our engineers the deep insights required to fully optimize our designs and overcome the numerous challenges caused by layout parasitics. Instead of treating parasitics as a black-box, ParagonX is shining light into the problem to allow us to truly understand what is going on, and to fix problems at their root cause.””

Alice Wang, Head of Edge Platform Architecture 

“Maxim and the Diakopto team, their products, and development process should serve as a model for how to develop modern EDA software in terms of speed, robustness, and attention to user needs.”

Kostas Pagiamtzis, Principal Analog Design Engineer

“ParagonX allows us to easily design and optimize the BEOL interconnect at an early design stage, devise physical implementation best practices, and pinpoint physical weak spots in complex layouts.”

Richard Fung, CEO
The Six Semiconductor

“ParagonX is crucial to the verification, analysis and optimization of very large power grids in SoCs with high performance analog circuitry. ParagonX accelerated the process of circuit debugging and optimization. With very little training, we were up and running and were quickly able to find and fix problems caused by parasitics.”

Bill Ellersick, CEO
Analog Circuit Works

“We appreciate how responsive and hands-on Diakopto is, which is frankly rare with EDA companies. And we do appreciate the expanse of your knowledge and your willingness to share upon consultation. These are the additional reasons (in addition to the value of ParagonX) to maintain business with Diakopto in my opinion.”

Haritha Eachempatti, SerDes Design Engineer
Ayar Labs

“Keep up the great work. The ultimate measure of success for any semiconductor company is not simulation time, but time-to-market and time-to-value. Interpreting and debugging post-layout simulations cause lengthy iterations that delay TTM. Good to see you and your team developing tools to overcome this critical bottleneck.”

Ted Tewksbury, CEO
Velodyne Lidar

“The quick diverse analysis and visual map of the resistive and capacitive parasitic paths in the layout save a lot of iteration time and hassles in the design. It has been a tremendous help in precision circuits where we have to match the phases and remove offsets.”

Shahrzad Naraghi, Founder
Legato Logic

“It just goes to show how important it is to really know and understand your circuit. If you don’t you just constantly “shoot in the dark” and it becomes very time consuming to fix your problems. Parasitics has always been difficult and countless home-grown tools have been created to help debug these issues. Now the SPEF/DSPF files are so huge that even these tools take forever to find the relevant parasitics. ParagonX really hits the mark in its speed and functionality. A designer can really understand, debug and fix these issues very efficiently!”

Dimitri Argyres, former Associate Technical Director/Master Engineer