ParagonX™
IC design and layout parasitics analysis, debugging and optimization
“With ParagonX, I can find a weak point on a 20GB extract in minutes, taking me right to the coordinates of the problematic area.”
– Ken Dyer, Principal Analog Design Engineer, Microsoft
ParagonX enhances existing EDA flows to help IC design, layout and CAD engineers quickly and easily find and fix root causes of parasitics-induced design problems. The tool addresses the increasing impact of layout parasitics on performance, precision, power, robustness, and reliability.
ParagonX is used earlier in the design process and identifies the few critical parasitic elements responsible for bottlenecks and weak points. The system reduces parasitics-related debugging and optimization to minutes or hours.
The ParagonX toolkit is integrated with easy-to-interpret visualization, and offers a comprehensive set of analyses, including:
- Resistance analysis
- Capacitance/coupling analysis
- RC delay, AC and transient simulations
- Net and device comparison and matching verification
- Netlist comparison
- QA and verification (extraction tools, settings, PDK versions, design revisions)
- Netlist structural analysis
Please contact us to learn more or to arrange for a ParagonX demonstration.