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PowerX is an EDA tool for the electrical simulation of metal interconnects of power semiconductor devices.

PowerX has two configurations (tiers) – PowerX Plus, and PowerX Pro:

  • PowerX Plus simulates DC current flow in source net, drain net, and multiple device channels (fingers), to calculate Rdson value, and all related characteristics.
  • PowerX Pro includes PowerX Plus functionality, and several more functions, to analyze all other characteristics important for power FET:
    • Top-level integration and routing analysis utilizing design intent and hierarchy information
    • Parasitic capacitance analysis, e.g. gate to drain capacitance, as well as capacitance-resistance trade-off optimization for low-capacitance devices,
    • Current sensing optimization (to locate the points for optimal placement of sense devices).
    • Minimum resistance path analysis,
    • Device characterization, to automatically calculate (using external SPICE simulations) device channel resistances,
    • Guard ring resistance and current density.

PowerX tool performs the following steps:

  • reads a DSPF file (extracted netlist) for power device or PMIC,
  • performs 2D mesh resistance extraction for user-specified layers and nets, using GDS file as an input,
  • “inserts” 2D meshes into DSPF file, replacing less accurate 1D resistors (or saves these meshes to a separate DSPF file),
  • performs electrical simulation of DC current flow between source and drain nets, connected by multiple device fingers (or channels),
  • calculates Rdson value, and reports contributions to Rdson by source net, drain net, devices, and by each layer in source and drain net,
  • helps analyze the uniformity of current flow in devices, multiple ports, and in source/drain interconnects,
  • visualizes distributions of different electrical characteristics, over the layout – potential distribution, current densities, and sensitivities (or contributions) of different parasitic resistors and polygons to the total Rdson.

As of now, PowerX performs meshing and electrical simulations as separate steps. A new netlist with 2D resistive meshes is saved as a new DSPF file, which is then read and analyzed by PowerX. In future, these two steps will be merged into one step.

PowerX allows to add layers not present in DSPF file to the meshing and electrical analysis. These may be RDL layer, packaging and PCB layers. These layers should be present in the main GDS file.

PowerX supports multiple ports on source and drain nets. By default, these ports are shorted together, for electrical analysis. Current through each port is calculated, reported, and visualized by PowerX. Optionally, the user can specify current boundary conditions (the total current is equally distributed across all ports on a net).

For 2D resistive mesh approach, ports should be defined as finite size (extended) 2D areas. These areas correspond to the interface areas for bonding wires, pads, balls, copper pillars, and other metal structures to connect the chip or device to the external world.

Device channel resistance – per instance (i.e. for the whole finger) – can be specified by the user in the input menu, or calculated automatically by external SPICE tool, using a function Generate device characterization file.

Devices are supposed to be operating in linear regime (i.e. large Vgs, and small Vds), where devices behave as constant resistors.

2D mesh extraction can be applied to one, or few top metal layers, that have complicated 2D shapes. Meshing of lower metal layers, that have a simple 1D geometry is not required. However, if necessary, the user can mesh all the layers, down to diffusion layer.

Large two-dimensional via layers should also be meshed, to properly simulate distributed current flow effects. Small vias are not meshed – only one parasitic resistor pr via is sufficient for small size vias. PowerX provides parameters to control the characteristic dimensions for via meshing.

Meshes in neighboring vias and metal should be “synchronized”, to avoid simulation artifacts – artificial current crowding effect, artificial spreading resistance, etc.

Polygon boundaries, metal slotting, and other geometric features are accurately described by triangular (finite element) mesh, generated by PowerX.

If the user specifies rules for EM (ElectroMigration) current densities, PowerX compares simulated current densities in metal and via resistors against these rules, and reports and visualizes EM violations. Also, a DRC-like marker database with AM violations can be generated, to be opened and browsed through over any layout editor system (Virtuoso, etc.).

The default mode for PowerX is a GUI mode.

PowerX Pro also provides a script, or batch mode – where all the steps and analysis functions can be scripted and run as a batch task. Batch mode is fully compatible with Python programming language. All functions in PowerX are Python functions, with all the results returned as data structures, that can be used, post-processed, and reported in the script.

All the results of electrical analysis in PowerX can be visualized – to display potential distributions, current densities, and sensitivities, over the layout. PowerX uses Klayout – a free open source layout editor and viewer – for its visualization. Klayout binary is provided as a standard part of PowerX installation package, it does not have to be installed separately from PowerX. Klayout is a very capable EDA tool, and PowerX customers are using it for many purposes other than visualization in PowerX.