ParagonX is an EDA tool offering a unique methodology and set of functionalities that dramatically accelerate IC design debugging and optimization. It helps users analyze, visualize and debug a broad range of problems caused by layout parasitics. The new methodology delivers unprecedented insights, speed of analysis and ease-of-use to significantly improve time-to-market, design performance, power efficiency, robustness and reliability.
ParagonX helps IC design, layout and CAD engineers very quickly and easily find root causes of parasitics-induced design problems. The key features and differentiators include:
- Intuitive: Unparalleled ease-of-use through an out-of-the-box experience that allows novice users to get started with minimal training. The tool does not require any complicated setup, configuration, CAD support or foundry qualification – “It just works”.
- Fast: Orders of magnitude faster than SPICE or other conventional EDA tools, even for very large netlists. ParagonX reduces parasitics-related IC debugging and optimization time from days or weeks down to minutes or hours, which is especially valuable during the tapeout phase.
- Insight to Drive Action: We deliver deep insights along with clear, visual and actionable results to empower engineers to quickly find and resolve design problems. Powered by an innovative platform technology that quickly pinpoints the few (out of thousands, millions or billions) parasitic elements that are responsible for bottlenecks, choke points or weak areas. This eliminates the manual, tedious and time-consuming task of debugging IC design problems caused by parasitic effects.
- Top-Hierarchy: We enable the analysis and verification of any level of IC design, including at the very top hierarchy. This is particularly useful to analyze large power, clock, signal, precision and sensitive nets for characteristics such as matching, delays, resistance, capacitive coupling, signal integrity, IR/EM, ESD, etc. The GUI remains very fast and responsive even for very large netlists (hundreds of GB in size) containing large number of nets and instances (millions or more).
- Non LVS-clean Methodology: Engineers are empowered to evaluate, analyze, verify and interactively improve layouts early on, including non-LVS clean designs. This is increasingly critical as design teams need to start layouts much earlier, to estimate/verify parasitics much earlier when no active devices or cells have been placed.
- Powerful “What-if” Analysis: This allows a faster exploration and understanding of the impact of various design characteristics, and the ability to locally iterate, trying out different options without making layout changes.
- Both GUI and Scripting Modes of Operation: The GUI enables interactive exploration of ParagonX analysis, especially useful for novice users, while scripting enables the efficient verification of all the characteristics of interest in a fully automated manner.
ParagonX has been adopted by over 35 industry-leading companies, for a wide range of design applications, including:
- High-speed SerDes
- Optical communications
- RF / 5G wireless
- Data converters
- AR / VR
- Image sensors
- MEMS / sensors
- Power management (PMICs)
- Low-power IoT
- AI / ML
ParagonX is foundry-agnostic and is being used for various technology nodes, including the latest technologies (16nm, 7nm, 5nm, 3nm, …), and older nodes (up to 0.35um).
The key functionalities of ParagonX include:
- Resistance analysis
- Capacitance / coupling analysis
- RC delay, AC and transient simulations
- Net and device comparison and matching verification
- Netlist comparison
- QA and verification (extraction tools, settings, PDK versions, design revisions)
- Netlist structural analysis
- And many more
Please contact us to learn more about ParagonX.
In addition to our flagship ParagonX tool and methodology, we have introduced several additional products to our customers. To learn more about these new products, please contact us.