Gate Resistance in IC design flow
Bizarre results for P2P resistance and current density (100x off) in on-chip ESD network simulations – why?
Your symmetric layouts are showing mismatches in SPICE simulations. What’s going on?
Circuit simulation and parasitics: do we need more speed, or more insight (or both)?
What are guardbands and guardbanding? (in engineering)
by Maxim Ershov (July 13, 2017)